How the logical shift operator works with concatenation?

SystemVerilog
, ,
1

please explain the execution of >> & << operator with concatenation in below example.
module abc;
bit[9:0] a,b;

initial begin
a = {$urandom, $urandom};
b = {<<{a}};
$display(“a =%b, b=%b”,a,b);
b = {>>{a}};
$display(“a =%b, b=%b”,a,b);
end

endmodule

output :-
xcelium> run
a =0110000111, b=1110000110
a =0110000111, b=0110000111
xmsim: *W,RNQUIE: Simulation is complete.
xcelium> exit

2

In reply to zalak patel:

Your code is functioning correctly as written. There are several conceptual issues with your code which you should fix:

  • The system function $urandom() returns a 32-bit integer. You are trying to concatenate two 32-bit integers and assign it to a 10 bit variable. This makes no sense and the concatenation achieves nothing.
  • You are using >>{} and <<{} as streaming operators, not as logical shift operators. Please refer to section 11.4.14 for an explanation of how these function.