How does the eda tool explain the simulation language, and gives the timing behavior of the digital circuit?
I want to know some base theory of eda simulation , are there any books to explain this? Thanks a lot!
In reply to wangdongya:
How does the eda tool explain the simulation language, and gives the timing behavior of the digital circuit?
I want to know some base theory of eda simulation , are there any books to explain this? Thanks a lot!
I don’t believe than any EDA vendor will disclose the methodology or tools they use to create the simulation environment. A vendor is required to abide by the requirements of the language definition, in this case, the 1800 specs.
As far as timing is concerned, SystemVerilog 1800’2017: 3.4.2 Simulation regions describes the requirements. I graphically expressed those concepts in my SVA book, a copy of those pages at http://systemverilog.us/vf/Timing_flow.pdf
With this understanding of those simulation regions, you can visualize an implementation with a language like C++ or Java, along with lots of loops and variables and classes.
If you want to understand a conceptual, but not implementation, of how concurrent assertions work, see my Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
wangdongya,
As Ben suggests, if you mean how the simulator conceptually models the timing of a circuit, I highly recommend what he does - trying to understand the event scheduling regions. See his diagram or (http://systemverilog.us/vf/Timing_flow.pdf) or the SystemVerilog 2017 LRM, Figure 4-1.
Understanding what happens in a time slot will provide a solid base knowledge, I think.
Ben, in your Timing_flow.pdf diagram/page, I think “Execution of events in the queue may re-trigger an earlier time slot.”, should be
“Execution of events in the queue may re-trigger an earlier event region.”
I only bring this up here, because of some confusion I ran into with the terminology of ‘time slots’, ‘time steps’, and other terms in describing event scheduling, as I asked here:
In reply to ljepson74:
“Execution of events in the queue may re-trigger an earlier time slot.”,
You may be right. From the diagram, an action block may change a variable that is used in a combinational logic (like in always_comb statement. But nonblocking assignments (e.g., a <= b) is evaluated in the Active Region, but does not pick up the 2nd iteration from the action block. consider
module top;
logic clk=0, a;
logic w=1'b1, qw, y=1'b1;
int q, qin, k;
always_comb w= y; // y is updated by the action block at time 90
// qw takes the value of y before the update
// though there is an iteration into th Active region by the action block
ap_w: assert property(1 |-> ##4 1) y =0;;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
always_ff @(posedge clk) begin
qw <= w;
end
http://SystemVerilog.us/vf/regions2.sv
1800’2017 provides the following regards to simulation regions:
- Figure 4-1—Event scheduling regions
- 4.5 SystemVerilog simulation reference algorithm
My diagram was more of a way to relate design blocks to regions.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
See Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy