Hi,
I wrote 100's of assertions to check for the connectivity / some conditions while running the simulations one assertions is not hitting (the condition/ signal name I wrote in that assertions is not available in that module) as I wrote bulk of assertions I don't know how to find the uncovered assertion. Is there any method to know whether the assertions is covered/ hitting or not. can you please guide me how to find the uncovered assertions.
Thanks in advance
Harshavardhan