In modern SOC designs there will be lot IPs that needs to be stitched(instantiated) at the SOC top level which will be written using either systemverilog or verilog. As IP counts are high, using name based instantiation is tedious and error prone. So is there any new methods followed in industries.
Typically there are tens of thousands of connections at the top level. It is almost impossible to get
this correct when done manually. Companies typically develop internal tools that help to create this
top level SOC. (including the instantiations and connections). The input to these tools could be some
tabular inputs that can be reviewed easily.
In addition to instantiations and connections there will be a minimal amount of glue logic. For example
there could be clock gating logic at the top level.
There are also formal apps that can be used to verify this connectivity.
Logie Ramachandran
Verikwest Systems Inc
In reply to logie:
I’m not exactly sure what “methods” you are looking for. From a language point of view, there are interfaces and wildcard port connections that reduce the amount of typing required to make connections. Editors like emacs have automations that help make module instantiations. And there are graphical tools that let you draw block-level diagrams/schematics.