How to instantiate an IP using package with different parameter values

SystemVerilog
,
1

Hi

We have an IP in which all its structs and parameters are defined in a package (each design *SV file of the IP imports the package).
We need to instantiate this IP more than once in our test bench, each time with a different set of parameters.
The problem is that we can not override the parameter’s values from the test bench becuase they are defined inside the package.

What is the way to override the parameters values from the test bench?

2

In reply to drorb:

SystemVerilog packages are global definitions; you cannot override the them.

You can set up the IP to use a package as default parameter types and values, and then when you instantiate the IP, you can override them on a per instance basis.

package global;
  typedef int Word_t;
  parameter int SIZE = 123;
endpackage
module IP();
  import global::*;
  parameter int SIZE = global::SIZE;
  Word_t array[SIZE];
endmodule

The parameter SIZE declaration in IP prevents importing global::SIZE. Now when you instantiate IP, you can override SIZE. I’m assuming you only need to override values, but you can use the same mechanism with parameter types.

3

In reply to dave_59:

Thanks!

Can this work with packed SystemVerilog struct ?
For example can parameters A,B be overriden in module IP?

package global;
   parameter A = 1;
   parameter B = 2;
  
  typedef struct packed  {
    logic [A-1:0] 		field1;
    logic [B-1:0] 		field2;
  } test_t;

endpackage