How to implement soft constraint without soft keyword

SystemVerilog
,
1

class demo;

rand bit cfg_en;
rand int idx_range;

constraint ex {
soft cfg_en == 0;
(!cfg_en) → (idx_range inside {[1:100]});
}

endclass

What is the workaround for soft constraint without disabling constraint.

2

In reply to uvm_novice:

Hard to answer without knowing all the other constraints involved. But normally you would disable, override, to completely rewrite your constraint expressions to handle this.