How to implement randomize() in verilog?

SystemVerilog
1

I have ModelSim, so I can’t use randomize in my code.

I have to implement randomize() on a transaction class (which extends uvm_sequence_item). How can I do it in verilog using $rand()?

2

In reply to saritr:

I have ModelSim, so I can’t use randomize in my code.
I have to implement randomize() on a transaction class (which extends uvm_sequence_item). How can I do it in verilog using $rand()?

Hi saritr. Since ModelSim does not support the randomize() function / method, you will need to implement that functionality in your class using older Verilog system tasks like $urandom_range and $urandom. For example:

class a;
    int unsigned b;

    function void my_randomize;
        b = $urandom;
    endfunction : my_randomize
endclass : a

module testbench;
    a a_h;

    initial
    begin
        a_h = new;

        repeat (3)
        begin
            a_h.my_randomize;
            $display ("a_h.b = %d", a_h.b);
        end
    end
endmodule : testbench
3

In reply to sbellock:

What if b defiition is:
bit [7:0] b

How can I random it?

4

In reply to saritr:

Then you would want something like

class a;
    bit [7:0] b [];

    function void my_randomize;
        foreach (b[index])
        begin
            b[index] = $urandom;
        end
    endfunction : my_randomize
endclass : a

module testbench;
    a a_h;

    initial
    begin
        a_h = new;
        a_h.b = new[5];

        repeat (2)
        begin
            a_h.my_randomize;
            $display ("a_h.b = %p", a_h.b);
        end
    end
endmodule : testbench

$urandom works OK for generating fairly unconstrained random bits, but if you need more constraints then the randomize() method is the way to go.