I needed to implement assertion on
Verilog Timing function such As
$width (negedge we_n &&& a_wire, tWP_min, 0, notif_err_twp);
or $setup (cle, posedge we_n &&& a_wire, tCLS_min, notif_err_tcls);
i implemented above function in assertion as
//FOR width //////////////////////////
always@(negedge we_n )
begin
if(a_wire)
#time_limit
->event_time;
end
property time_check (start,time_limit)
time curr_time;
@(start)(1, curr_time = $time) |->(($time - curr_time) > (tSetup + tHold));
endproperty
property width_chk
time_check(event_time,tWP_min)
endproperty
assert property(width_chk);
//FOR Setup/////////////////
always@(posedge we_n )
begin
if(a_wire)
#time_limit
->event_time;
end
property time_check (start,stop,time_limit)
time curr_time;
@(start)(1, curr_time = $time) |->@(stop)(($time - curr_time) > (tSetup + tHold));
endproperty
property width_chk
time_check(cle,event_time,tCLS_min)
endproperty
assert property(width_chk);
In above codes i am facing Segmentation Error and i also required help about “&&&” sign ?
plz help me in it or suggest an other way…thanks.