How to handle delay in Verilog Behavioral Modeling?

SystemVerilog
,
1

Hi, can someone help me to solve those delay issue in Verilog Behavioral Modeling?

1.Why the two kinds of stimulus(typeI:+define+DELAY_12, typeII:`else) yield different results? Specificly for typeI stimulus, typeI waveform ; for typeII stimulus, typeII waveform

2.Is there some options for simulator to propagate the delay transparently?

module tb;
  reg ci;
  reg [3:0] a, b;
  wire co;
  wire [3:0] sum;
  
  adder_t4 adder(.co(co),
                 .sum(sum),
                 .a(a),
                 .b(b),
                 .ci(ci));
  
  initial begin
    {a,b,ci} = 0;
    #15 a = 4'hA;
    `ifdef DELAY_12
      #12 b = 4'h3;
    `else
      #11 b = 4'h3;
       #1 b = 4'h3;    
    `endif
    #2 a = 4'h2;
    #2 a = 4'hF;
    #50 $finish;
  end
  
  initial begin
    $dumpfile("test.vcd");
    $dumpvars(0, tb);
  end

module adder_t4(co, sum, a, b, ci);
  output co;
  output [3:0] sum;
  input [3:0] a, b;
  input ci;
  
  assign #12 {co, sum} = a + b + ci;
endmodule
2

In reply to mlsxdx:

Section 10.3.3 Continuous assignment delays describes the behavior you see. This is known as an inertial delay. To get the behavior you are looking for, use a non-blocking assignment which has transport delay.

3

In reply to dave_59:

Thanks for your explanation. Now I know it is inertial delay for continuous assignment.
For this specific case, by using non-blocking assignment, I am able to see all the input update(<12) propagating to output.