How to handle delay in the assertion

SystemVerilog
,
1

Hi ,

I have written an assertion as following,

sequence tx_count_package_lenreset_1; // 20-39 Lanes
@(posedge txclk1)
($rose(strobelane1_txactive));
endsequence

Problem facing :

→ there is an delay after the posedge clock to rise of strobelane1_txactive.
→ The delay difference is about 10ps from the posedge to the rise of the signal.
→ So,Because this sequence “tx_count_package_lenreset_1” is never been high.
→ I am using this sequence in another property which never triggers because of this issue.

My view : Something like this, //// Compilation error…
sequence tx_count_package_lenreset_1; // 20-39 Lanes
@(posedge txclk1)
##10ps; ($rose(strobelane1_txactive));
endsequence

→ I would like to know how to handle it.

-Regards,
-Raja.

2

It would be easier to answer this question if you can provide a timing diagram showing the relationship between txclk1 and strobelane1_txactive.
Are you saying that strobelane1_txactive does not last a full cycle of txclk1?
How is that signal generated? From what you express, it looks like it maybe something like this (I am emulating any gate delays):

module strobe; 
  bit txclk1, lane1, strobelane1_txactive;
  always @(posedge txclk1) begin 
   	#10ps strobelane1_txactive <= lane1; 
  end

But you say “Because this sequence “tx_count_package_lenreset_1” is never been high.”
So solution for you is to add auxiliary code to see the pulse. Perhaps something this maybe be what you need. I basically use a multi-clocked sequence; however, I am not clear of your requirements, but this should get you thinking in another direction for a solution.

module strobe; 
  bit txclk1, lane1, strobelane1_txactive, clk11;
  always @(posedge txclk1) begin 
   	#10ps strobelane1_txactive <= lane1; 
   	#1ps  clk11 <= txclk1; 
  end 
  
  sequence tx_count_package_lenreset_1; // 20-39 Lanes 
    @(posedge txclk1) strobelane1_txactive ==1'b0 ##0 @clk11 strobelane1_txactive ==1'b1;
  endsequence 
	
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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