How to handle assertion disables in gate-level simulation?

SystemVerilog
1

Hi,

I’m running into an issue re-using assertions in gate-level sims.

At the top level of our testbench, I have a number of control bits that are used as the disable conditions for our assertions. The problem is that in gate-level sim, all those signals are gone, presumably as they don’t connect to the design.

SOME_ASSERT_CHECK : assert property(some_assertion(**disable_bit**, argumentX, argumentY) );

Right now I’m working around the issue by defining a series of gate-sim specific behavioral tasks that uses $asserton and $assertoff to control assertions, but I have to write one statement for each and every assertion out there and it seems to me that there surely must be a better and cleaner way to do this.

Any recommendations on how one can go about controlling assertion disables that functions smoothly both in regular sim and gate-level sim?

Thanks!

2

In reply to silverace99:

You might want to look at your tools documentation for disabling assertions on the command line with wildcards.

3

Does it help to use an command line option “+DISABLE_IN_GLS”. When you run simulation with this command line option, the assertion will be disabled.

disable_bit = disable_bit || $test$plusargs(“DISABLE_IN_GLS”);

4

In reply to Lina.Lin:

Does it help to use an command line option “+DISABLE_IN_GLS”. When you run simulation with this command line option, the assertion will be disabled.
disable_bit = disable_bit || $test$plusargs(“DISABLE_IN_GLS”);

Well actually, i want to run the assertion in GLS also.

But your idea seems like it could work if i use plusargs to replace the disable bits. Something like


SOME_ASSERT_CHECK : assert property(some_assertion($value$plusargs("TURN_OFF_THIS_ASSERT_TYPE"), argumentX, argumentY) );

Seems like a reasonably clean solution. But I’m happy to hear other thoughts!