How to get enum value

SystemVerilog
1

module enum_data();

bit [4:0] jd;
typedef enum { red[4], green[4], blue[4], yellow[4], white[4], black[4] } Colors;

Colors Lcolors;
initial begin

jd=$random;
Lcolors = red0;

$display (" Lcolors = %s…%d", Lcolors,jd);
end
endmodule

How can i get following result using loop?
for jd = 0 , Lcolors=red0
jd = 1 , Lcolors=red1
jd = 2, Lcolors=red3 … so on…

Thanks.

2

In reply to jd prajapati:

static cast


module automatic test;
  	bit [4:0] jd;
	typedef enum { red[4], green[4], blue[4], yellow[4], white[4], black[4] } Colors;
	Colors Lcolors;
 
	initial begin
	jd=$random;
	Lcolors = red0;
	$display (" Lcolors = %s.....%d", Lcolors,jd); 
        for(int i = 0; i < 24; i++) begin
            Lcolors = Colors'(i);
            $display("loop_%0d : %s", i, Lcolors);
        end
    end
endmodule