How to force/deposit string path in system verilog?

SystemVerilog
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1

Hi all,

I want to create SV based APIs which should have input arguments as string path and value for force/deposit specified path. As per my understanding, UVM provides support of uvm_hdl_force/uvm_hdl_deposit. But i have SV based environment and i want to achieve same with force/release keyword. My actual problem/question is, how can i convert string path into variable instance?
Does anyone has any better approach for this?

Thanks and Regards,
Mitesh Patel

2

In reply to mitesh.patel:

There is nothing within the SystemVerilog language that allowed you to convert a string to identifier reference. The only possibility involves use of the VPI C interface.

Since you are already using SystemVerilog, there is nothing preventing you from using UVM and its VPI code. You can even specifically import the routines you want to use without importing the whole package.

Other options are using tool specific commands to do the force, or copying the UVM code for your own use (I’m mentioning that, but not recommending that).

3

In reply to dave_59:

Thanks dave. I understood that, string datatype can not converted to integral type/reg only using system verilog. But can i do reverse? I have instance path(reg/intergral type) and can i convert that in to string using some beauty of system-verilog? Please suggest if any alternate ways are there to do this?

Thanks and Regards,
Mitesh Patel

4

In reply to mitesh.patel:

There is no way in SystemVerilog to do this without using the VPI with C code.

5

In reply to dave_59:

Hi Dave,

Thanks for the response.
Actually, I have tried to create macro to covert integral type(instance path) into string and somehow i achieved it. Please see the snippet of the code.

   string hpath;
   `define STRINGIFY(x) $sformatf("%0s", `"x`")
   
   `define DO_FORCE(HPATH, val)\
     `ifdef SV\
        force HPATH = ``val;\
     `elsif UVM\
        hpath = `STRINGIFY(HPATH);\
        $display("%0s", hpath); \
        if(!uvm_hdl_check_path(hpath))\
          $error("ABCD :: %s path not found", hpath);\
        uvm_hdl_force(hpath, ``val);\
     `endif\

     `DO_FORCE(top.chip.block,10);

Is this approach is okay to use? can you feel any issue with this? Please suggest.
Please note that, define SV/UVM is defined based on environment type. (Eg, +define+SV or +define+UVM). Here, i want to make common support, which can be use by SV or UVM environment.

Thanks and Regards,
Mitesh Patel

6

In reply to mitesh.patel:

After seeing some code, your second (reverse) question makes more sense. What you wrote should work, but there are some differences in terminology I would have used to explain it.

By using macros, you are converting arbitrary text into strings and identifiers. The macro pre-processor does not know anything about SystemVerilog identifiers. Only after processing the text macros does the SystemVerilog parser look at the code

7

In reply to dave_59:

okay. Thanks for responses.