How to find realtime variable is odd or even in system verilog?

SystemVerilog
1

I would like to know if a real time variable is odd or even
for example

realtime a;
bit b;

b = a % 2; //( modulus will give remainder if remainder is 0 - it is even , else odd)
but I am not able to get the modulus of realtime variable a

Is there any other way to find whether a is odd or even.

Thanks,
Sunanda

2

In reply to sunanda_kommi:

This is not a SystemVerilog question. Even and odd are only defined for integers (there is no widely accepted definition for real values).

3

In reply to dave_59:

I have code like below

realtime clk_period1;
realtime clk_period2;
realtime clk_time_t;

@posedge(input_clk);
clk_period1 = $realtime;
@posedge(input_clk);
clk_period2 = $realtime;

clk_time_t = clk_period2 - clk_period1;

// Now i need to generate twice the frequency of first clock clk_time_t

fast_clk_time_t = clk_time_t /2 ;
//to generate clock , for posedge time and negedge time i again had to divide the fast_clk_time_t
// Now if fast_clk_time_t is odd value , I cannot generate accurate clock , So i wanted to know if there is any way to find odd or even value of realtime variable

let me know if you have any suggestion on this

Any way i can generate the faster clock accurately

Regards,
Sunanda

4

In reply to sunanda_kommi:

Do you know that $realtime returns an integer value? You could have a timescale of 1ns but a precision of 1ps. In that case clk_time_t could have a fractional component. You can check that there is no factional component by casting the value to an int, and then comparing the result to the original real. Then you can use the module operator on the int value.