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How to select from multiple drivers to same variable using assertions(I want to get a value for an o signal or variable from a specific driver based on an input)
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How to find from which driver getting value to variable using assertions(In most cases, only one driver can update or send data to o signals or o variables)
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How to confirm a single signal driven by multiple drivers by using assertions(Ex1, Ex2 are multiple drivers and Ex3 is single drivers)
Ex1: wire o = s ? a : 1’bz;
wire o = s ? b : 1’bz;
wire o = s ? c : 1’bz;
wire o = s ? d : 1’bz;
Ex2:
wire o = m ? n[0] : 1’bz;
wire o = m ? n[1] : 1’bz;
wire o = m ? n[2] : 1’bz;
wire o = m ? n[3] : 1’bz;
Ex3:
wire o = a? x: 1’bz;
Please help me in this Thanks in Advance
In reply to Subbi Reddy:
Assertions address the properties of the requirements?
What are your requirements?
From your code, it seems that you have 4 drivers (s[0:3])
enabling 4 signals (a, b, c, d) onto an output o.
So what are requirements?
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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In reply to ben@SystemVerilog.us:
Hi Ben,
Please take a look at the updated requirements and share your knowledge.
In reply to Subbi Reddy:
- How to select from multiple drivers to same variable using assertions(I want to get a value for an o signal or variable from a specific driver based on an input)
- How to find from which driver getting value to variable using assertions(In most cases, only one driver can update or send data to o signals or o variables)
- How to confirm a single signal driven by multiple drivers by using assertions(Ex1, Ex2 are multiple drivers and Ex3 is single drivers)
These are the assertions I see
module m;
wire a, b, c, d, ot;
bit[0:3] driver;
bit clk;
assign ot= driver[0] ? a : 1'bz;
assign ot= driver[1] ? b : 1'bz;
assign ot= driver[2] ? c : 1'bz;
assign ot= driver[3] ? d : 1'bz;
// driver has one 1 or is zero (Your item 3)
ap_one1or0: assert property(@(posedge clk) $onehot0(driver));
// expected output based on driver
ap_0: assert property(@(posedge clk) driver[0] |-> ot==a);
// same for the other indices
//..
ap_3: assert property(@(posedge clk) driver[3] |-> ot==d);
// Test for Z
ap_z: assert property(@(posedge clk) driver==0 |-> ot===1'bZ);
endmodule