In reply to saritr:
Am providing a possible metod to insure that check before proceeding.
This approach uses a master/slave relationship between 2 concurrent machines.
Apply this approach as you see fit.
For the record, I appreciated this concept in the design of a traffic light controller.
The problematic traffic light controller represented a model where the East-West and North-South FSMs are loosely tied, and there lies the source of errors such as both East-West and North-South lights turning GREEN in the same cycle.
To resolve this issue, a centralized architecture was used. The new design relies on the North-South FSM being the master controller. The East-West slave FSM makes an ew_green_request whenever it wants access to the light. That request is granted with the ew_green_grant handshake. It is provided by the North-South FSM when the North-South goes YELLOW. In addition, to maintain this centralized control, the North-South FSM will inform the East-West FSM to go RED with the ew_to_red_cmd command. That command is a function of the value of the emergency sensor, the value of the East-West sensor, and the length of time that East-West light stayed GREEN. A centralized North-South GREEN timer, instead of two independent timers, controls that time.
event req, ack;
virtual task run_phase(uvm_phase phase);
fork
begin : clock_c
forever begin
wait(vif.fact_log2_samp != fact_log2_samp_init);
for(int counter = 0; counter < 46; counter++) begin
check = 1'b0;
@(posedge vif.clk);
end
check =1'b1; // <--
end// forever
end// clock_c
begin : check_controller //---------------MASTER HANDSHAKE CONTROLLER --------------
@ req;
if(check) -> ack;
else begin
wait(check);
-> ack;
end
end // ---------------------------------------
begin : main_0
forever begin
mon_trx = tx_lin_int_transaction::type_id::create("mon_trx");
mon_trx.fact_log_2 = fact_log2_samp_init;
**wait (vif.xn_valid == 1'b1);**
#1; // NEED THIS?
-> req; // ------------- SLAVE ---------------
@ ack; // --------------------------------------
mon_trx.rand_data_xi = vif.xi;
mon_trx.rand_data_xq = vif.xq;
if (check == 1'b0)
mon_trx.check = FALSE;
else
fact_log2_samp_init = vif.fact_log2_samp;
$cast(t, mon_trx.clone());
//send transaction to scoreboard via TLM write()
ap.write(t);
wait (vif.xn_valid == 1'b0);
end// forever
end// main_0
join
endtask: run_phase