How to drive a weak pull up on an Open Drain, Active Low Dedicated IO pin

SystemVerilog
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1

So my design has a dedicated I/O pin which is open-drain, active-low.

Internally, the PAD is pulled to zero (pull enable is 1 and it is pulled to GND). This is an incorrect setting because then this input will always be active. Ideally the PAD should be pulled to supply.

Now this same PIN is pulled up on the test bench side to mimic an external pull up resistor.

pullup(INPUT1)

Now I want it to be weak pull up resistor so that this bug is exposed. The problem is,

pullup(weak1) (INPUT1) does not work in the sense that the PAD is not pulled to zero.

What is the best way to have a weak pull-up on this pin so that the internal pull down can be seen?

2

In reply to cooltoad:

For the situation you are describing, the DUT drives St0 or Pu0. The TB drives Pu1. So the resolved signal is St0 or PuX. You are going to have to provide an example to make is clear what you are looking to see.