How to drive output clockvar which is a net?

SystemVerilog
,
1

Consider the following clocking block definition ::


 
 logic [1:0] a ;
 logic [2:0] out;
 
 wire  [1:0] b ;
 
 clocking  cb @( posedge clk );
    default input  #1step  output #2 ;
     
    output  a  , b ;
     input  out ;
 endclocking

Typically if user wants to drive output clockvar ’ a ’ which is actually a variable we use :


  //  Within  any  procedural  block  
      @( cb );
      cb.a <= 2 ;

To drive clockvar ’ b ’ which is a net ( so I can’t drive procedurally ) , I would be using :assign cb.b = …

Typically we wait for clocking block event @( cb ) before driving output clockvars ,
how could I incorporate @( cb ) with assign statement to drive output clockvar b ?

The other question is how could I drive output clockvar b at the same time as I am driving clockvar a i.e How do I synchronize the two drives ?

2

In reply to Have_A_Doubt:

Clocking block output variables are always written using procedural drive statements—it does not matter if the target signal is a variable or a net. You cannot write to a clocking block output variable with any other kind of assignment.