How does verilog deal with the fact that it doesn't allow user defined types

SystemVerilog
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Hello everyone,
I am sorry if my question seems out of the topic, but it’s just that there was no verilog forum.

Every digital designer will find himself/herself in need to define new types, something which is possible in both vhdl and systemverilog, but not in verilog. do you have any idea how verilog programmers deal with this problem.?

Multiple thanks in advance.

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In reply to Yasmine4:

How did Verilog designers deal with the lack of user-defined types? Well, we typed more, and used cut/paste more. And we ran into more dumb keyboarding mistakes, and cut/paste errors more often than we do today when using SystemVerilog.

To be truthful - for me at least - user-defined types are a nice to have, but I could still live without them. Multi-dimensional arrays as first class citizens in SystemVerilog? I could never go back to using Verilog without these multi-dimensional arrays.

Regards,

Mark

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In reply to Yasmine4:

do you have any idea how verilog programmers deal with this problem.?

They move to SystemVerilog. It’s been widely available for over a decade now in ASIC development. All of the major FPGA development tools have broad synthesis support of user defined type between 5-10 years. Why not move up from Verilog?

Dave

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In reply to Mark Curry:

In reply to Yasmine4:
How did Verilog designers deal with the lack of user-defined types? Well, we typed more, and used cut/paste more. And we ran into more dumb keyboarding mistakes, and cut/paste errors more often than we do today when using SystemVerilog.
To be truthful - for me at least - user-defined types are a nice to have, but I could still live without them. Multi-dimensional arrays as first class citizens in SystemVerilog? I could never go back to using Verilog without these multi-dimensional arrays.
Regards,
Mark

Thank you for your answer Mark,

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In reply to dave_59:

In reply to Yasmine4:
They move to SystemVerilog. It’s been widely available for over a decade now in ASIC development. All of the major FPGA development tools have broad synthesis support of user defined type between 5-10 years. Why not move up from Verilog?
Dave

Thank you dave, although moving from a language to another is not as simple as it looks, given the fact that there is a lot of old code that is still being used.

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In reply to Yasmine4:

With the exception of new reserved keywords, Verilog is SystemVerilog. So it’s very easy to introduce SystemVerilog constructs within it.