D- Flip Flop using blocking assignments
module RisingEdge_DFlipFlop_SyncReset(D,clk,sync_reset,Q);
input D; // Data input
input clk; // clock input
input sync_reset; // synchronous reset
output reg Q; // output Q
always @(posedge clk)
begin
if(sync_reset==1'b1)
Q = 1'b0;
else
Q = D;
end
endmodul
e
D Flip Flop using Non Blocking assignmentsmodule RisingEdge_DFlipFlop_SyncReset(D,clk,sync_reset,Q);
input D; // Data input
input clk; // clock input
input sync_reset; // synchronous reset
output reg Q; // output Q
always @(posedge clk)
begin
if(sync_reset==1'b1)
Q <= 1'b0;
else
Q <= D;
end
endmodule
How does above code differ with respect to synthesis . To what logic does above code with blocking assignment get synthesized to .
