Hi All,
When I was learning SystemVerilog Scheduling, I don’t understand some part of the scheduling chart. I saw for each region from active to re-inactive, there is a path to loop back. I don’t understand how Observed region can trigger a loop back to Active region. I believe no actions in the observed region can change any signal value, even the initialization is only changing the local variable within the property.
Thanks in advance.
In reply to zhuyuxiong:
When I was learning SystemVerilog Scheduling, I don’t understand some part of the scheduling chart. I saw for each region from active to re-inactive, there is a path to loop back. I don’t understand how Observed region can trigger a loop back to Active region. I believe no actions in the observed region can change any signal value, even the initialization is only changing the local variable within the property.
I described the SystemVerilog scheduling events in my SVA book. Below is a link to that page
My chart demonstrates graphically when values are evaluated and assigned.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
In reply to ben@SystemVerilog.us:
Thanks Ben, I agree with you because I also think the Observed region shouldn’t have loop back. But do you know why there is this loop back in the IEEE standard 1800-2005? Is it because that they just want to leave a hook which could be used once needed for future systemverilog standard?
Ethan
In reply to zhuyuxiong:
consider the following example:
With ap: assert property($rose(a) |-> 1) flip(e);
“e” changes in the Reactive Region.
From the Reactive Region you loop back to the Active Region when you recalculate
assign b= e; // if (e) changes
There is no reassignment in the NBA. When “e” changes in the 2nd loop through the Active, the always_ff @(posedge clk) d <= e; does not get reassigned.
I am really part of SV-AC (assertion committee); there is another committee that address those other timing and language issues. But I do see a need to loop back.
import uvm_pkg::*; `include "uvm_macros.svh"
module top;
bit clk, a;
logic b,c, d, e=1;
default clocking @(posedge clk); endclocking
initial forever #10 clk=!clk;
always_ff @(posedge clk) begin
d <= e;
end
assign b= e;
function void flip(logic w);
e = !w;
endfunction
ap: assert property($rose(a) |-> 1) flip(e);
initial begin
repeat(200) begin
@(posedge clk);
if (!randomize(a) with
{ a dist {1'b1:=1, 1'b0:=2};
}) `uvm_error("MYERR", "This is a randomize error")
end
$stop;
end
endmodule
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
In reply to ben@SystemVerilog.us:
I understand that there should be a loop back from reactive region, but I was talking about the loop from Observed region. In the related section of your book there is no such a loop from Observed region, but it does exist in the IEEE standard.
Thanks