In reply to arquer:
Connecting up a SystemVerilog interface to bidi signals is a bit tricky. But in fact there's a way to accomplish it that works in both simulation and synthesis (it works under Xilinx for Vivado at least). It requires a few extra steps but works reliably.
We create a "bidi_feedthru" module:
parameter WIDTH = 64
inout wire [ WIDTH - 1 : 0 ] p0,
inout wire [ WIDTH - 1 : 0 ] p1
tran t1[ WIDTH - 1 : 0 ]( p1, p0 );
Now, at the top-level of our design, we have a standard "wire" bidi bus:
inout wire [ 7 : 0 ] DRAM_DQS,
inout wire [ 63 : 0 ] DRAM_DQ
We wish to hookup the bidi wires to an interface "ddr_if". Do so like thus:
bidi_feedthru #( .WIDTH( 8 ) ) dqs_alias( DRAM_DQS, ddr_if.dqs );
bidi_feedthru #( .WIDTH( 64 ) ) dq_alias( DRAM_DQ, ddr_if.dq );
As the instance name implies, what we're looking for here is a (non-existing SystemVerilog feature) of a "net alias" that works with interface members. This trick fills the language hole with a few extra steps.
The above will connect up your bidi signals to the interface - and it works both in simulation and synthesis (at least for Vivado)