Hi All,
MY design is as follows…
- Interface has all the port signals and parameters use for design and verification environment.
- In test bench, i have passed interface instance into DUT and test(verification environment top).
- The static interface instance handle has been passed to verification environment from test and assign to the virtual interface handle
- The virtual interface handle has been passed to sub classes(stimulus,driver,monitor…etc)
- The error is throwing at the place where i am using virtual interface parameter in stimulus class for specifying range in signal declaration
Code as below
mem_interface.sv:
interface mem_interface #(parameter ADDRESS_WIDTH=10’d10,DATA_WIDTH=32’d32)(input logic clk);
//IO declarations
logic rst,we;
logic [(DATA_WIDTH-1):0] data_in;
logic [(ADDRESS_WIDTH-1):0] address;
logic [(DATA_WIDTH-1):0] data_out;
endinterface
testbench.sv
module memory_tb#(parameter ADDRESS_WIDTH=10’d10,DATA_WIDTH=32’d32);
//IO declarations
//clock will be passing to design and test environment
bit clk;
// interface instantiation
mem_interface #(10,32) mem_intf(.clk(clk));
//DUT instantiation
memory mem_dut(mem_intf);
//passing instance to test environment
memory_test test(mem_intf);
//clock generation
always #5 clk = ~clk;
initial begin
clk = 1’d0;
end
endmodule
memory_test.sv:
program memory_test(mem_interface test_intf);
//environment instance
memory_env env;
task run();
//calling env method
env.run();
#100;
$finish;
endtask
initial begin
//passing interface instance to environment
env=new(test_intf);
end
endprogram
memory_env.sv:
include "memory_driver.sv"
include “memory_monitor.sv”
include "memory_scoreboard.sv"
include “memory_stimulus.sv”
class memory_env;
//interface instance
virtual mem_interface #(10,32) vir_intf;
//class instances
memory_driver drv;
memory_monitor mon;
memory_scoreboard scb;
memory_stimulus stim;
function new(virtual mem_interface #(10,32) test_intf);
this.vir_intf = test_intf;
drv=new(test_intf);
mon=new(test_intf);
scb=new(test_intf);
stim=new(test_intf);
endfunction
task run();
//driving stim to dut
drv.drv_stim();
//collect results from dut
mon.collect_res();
//checking results in scoreboard
scb.check_res();
endtask
endclass
class memory_stimulus;
//declaration of virtual interface handle
virtual mem_interface #(10,32) vir_intf;
//constructor
function new(virtual mem_interface #(10,32) test_intf);
this.vir_intf = test_intf;
endfunction
//IO declarations
rand bit rst,we;
rand bit [(vir_intf.DATA_WIDTH-1):0] data_in;
endclass
This is the code for reference purpose to solve my issue. could you please anyone share the links about how do i access parameter which has been defined in interface in any module/verification environment by using instance??