How to do bitwise or on unpacked array

SystemVerilog
,
1

Hi,

for packed array it’s easy to do bitwise or:


var logic [7:0] data;
var logic is_one;

assign is_one = |data;

how can I do it with unpacked array?


var logic data [8];
var logic is_one;

assign is_one = ??????;
2

In reply to yakir_mishli:

Use the or reduction method (7.12.3 Array reduction methods).

assign is_one = data.or();
3

In reply to dave_59:

I know that could be tool related but to avoid facing some tools issues since continuous assignment could not work with array reduction, so i would suggest using

always_comb
   is_one = array.or();

I know is only tool related and this forum will not take care of tool issues but just to clarify it.
Regards

4

In reply to Rsignori92:

Thanks for the clarification. To be on safe side I will use always_comp.