How to deal with reset in sv test environment?

SystemVerilog
1

If I have 10 transactions and if I apply reset at middle of any transaction,then output and inputs should become zero and after reset becomes low the transactions should continue.how to do this

2

declare 1 variable globally (like rst_glbl)

Now assign your reset variable to this global variable in top module.
like :
assign rst_glbl = reset;

Now in your transaction class make constraint
constraint rst_var{if(rst_glbl) {data_in==0; wr_addr==0; rd_addr==0;}}

3

In reply to Charan123:

Your question has a lot of missing information. Do you want the transaction that was reset in the middle to start over, or continue where it left off. A lot of that depends on the interface protocol, and how you have coded your transaction driver.

Typically, your driver is written as a finite-state-machine and you just need to add the states needed to deal with reset

typedef enum {IDLE, DRIVING, RESET) drive_e;

drive_e DRIVER_STATE;

forever begin
     @(posedge clk or posedge reset) 
     if (reset) begin
        ... drive inputs to 0;
        if (DRIVER_STATE != IDLE) DRIVER_STATE <= RESET;
     end else begin
     case (DRIVER_STATE)
     IDLE:
4

Thanks a lot to both of u…both of the solutions worked out.