Hi,
I am very familiar with synthesizable Verilog but am new to System Verilog and I am trying to see if it has some features that I could use to clean up my testbench. Specifically I have a channel model which will be used to simulate various different channels in different testcases. Currently it is implemented as a parametrized module but it is somewhat unwieldy in that there are many parameters of different types (some are literals, some are filenames etc) and they all need to be changed for each new channel. What I would like to be able to do would be to create a new Object/Structure which would contain all these parameters as fields and then be able to pass just a single Object/Structure to my channel module as a parameter. Does anyone know if this is possible with SV and if so how is it done? Essentially what I want to do is replace something like this:
channel #(.MXCOEFS(32768),
.comp_dly_ns(loc_cbl_dly),
.comp_inv_en(loc_cbl_inv),
.coefs_dir(coefs_dir),
.coefs_file(loc_coefs_file)) loc_channel (
.ip(loc_tx_symbols),
.rx_clk(loc_clk),
.
.
.op(loc_op)
);
With something cleaner like:
channel #(.channel_type(short_channel)) loc_channel (
.ip(loc_tx_symbols),
.rx_clk(loc_clk),
.
.
.op(loc_op)
);
Where short_channel is a Structure/Object with many fields of different types
Thanks