How to create a one-hot coverpoint on a parameterized signal?

SystemVerilog
,
1

Hi,

I would like to find out a way to create a one-hot coverpoint on a parameterized signal.



If this is my signal:
logic[WIDTH-1:0]   my_sig;

How can I implement a covergroup/coverpoint to cover one-hot?

Any help is much appreciated.

Thanks,
Madhu

2

In reply to mseyunni:

You can have a look at this article http://www.amiq.com/consulting/2015/09/18/functional-coverage-patterns-bitwise-coverage/ which has lots of interesting ways of writing fcov for bitwise patterns you may be able to adapt it to your requirements.

Also this https://www.amiq.com/consulting/2018/01/15/how-to-alternative-ways-to-implement-bitwise-coverage/ may be useful.

HTH,
-R