How to create a 0ns glitch?

SystemVerilog
,
1

I want to create 0 time glitch that is in the same time stamp i want to see all three(1-> 0 → 1) transitions. Can any one help/ provide me a example how to meet the expectation?

2

In reply to Kkss:

bit glitch;
initial begin
  glitch = 1;
  #10 glitch <= 0;
  @glitch glitch <= 1;
end
3

In reply to dave_59:

Hi Dave,
I have created below small example, but not able to see glitch!
Not sure if I understood it correct, can you please advice? what else is needed?

module top();

bit glitch;
initial begin
  glitch = 1;
  #10 glitch <= 0;
  @glitch glitch <= 1;
  #10ns;
  $display("Test is ending");
  $finish;
end

initial begin
  $dumpvars;
  $dumpfile("glitch.vcd");
end

endmodule : top

Thank you.
Mega

4

In reply to megamind:

The VCD text files are too basic to capture glitches. You would have to use the waveform dumper that comes with your tool. You can also write

always_comb $display("Glitch is %b at time %t",glitch,$realtime);
5

In reply to dave_59:

Thank you.