How to convert a always block in to task

SystemVerilog
1

Hi,
I was assigned a task to convert the always block inside the module to task in a separate file,
Coding :


always @(posedge s_axi_aclk)
  begin
     if (axi_access_sm == WRITE) begin
        if (!axi_status[4]) begin
           s_axi_bready  <= 1'b1;
           if (s_axi_bvalid == 1'b1 && s_axi_bready) begin
              axi_status[4] <= 1;
              s_axi_bready     <= 0;
           end
        end
     end
     else begin
        s_axi_bready     <= 0;
        axi_status[4]    <= 0;
     end
  end

I have converted the above always block to task as


task write_resp();
forever @(posedge s_axi_aclk) begin
       if (axi_access_sm == WRITE) begin
         if (!axi_status[4]) begin
              s_axi_bready  <= 1'b1;
           if (s_axi_bvalid == 1'b1 && s_axi_bready) begin
               axi_status[4] <= 1;
               s_axi_bready     <= 0;
           end
         end
       end
       else begin
         s_axi_bready     <= 0;
         axi_status[4]    <= 0;
       end
     end
 endtask

I am having a connecting issue itseems, Kindly help me how to call this task inside the module

2

In reply to Elamparethy:

I am having a connecting issue itseems, Kindly help me how to call this task inside the module

You can call the task from within an initial block.
If the task is called this way from inside the module then I do not see or understand the connectivity issue.
Why would you want to do a always block from within a task?

3

Thanks for reply Ben, i will apply it in code and let you know.
I am having task to convert module based to class based that’s why.

4

In reply to Elamparethy:

Converting a testbench to class based is a much bigger topic than your original question.
You can’t call a task in a class before it has been constructed.

The point of having a class based testbench is taking advantage of Object Oriented Programming which allowed you to utilize base class libraries and extend the classes you write for re-usability.

The UVM provides a framework for dealing with constructing a trestbench designed for re-usablility. Without knowing what kind of class-based methodology you are using and the "connectivity problems you are facing, it is difficult to help you.

5

thanks for reply dave_59
I have assigned to do the following task step by step.

  1. We are having a module, which has always block, we need to convert that always block to task which triggers the test.
  2. we are converting that task to class based
  3. we are extending that class with uvm_test
  4. we need to run that particular test by calling the testname.

So far, we have converted that always block to task (in step 1) but when we run we are getting the ERROR : SIGNAL SIGSEGV RECEIVED

6

May be this paper can help you

https://www.techonline.com/tech-papers/efficient-migration-of-verilog-testbenches-to-uvm/