How to control r_wn bit ==1 from test case

SystemVerilog
, ,
1

Hi;

I have one transaction class.

class transaction;
  rand bit r_wn;
endclass

This is being generated in generator :

class gen(…);
transaction trans;
this trans is new() and then sent to driver.
endclass

Now from testcase I want to send 5 transactions with r_wn ==1 how to implement this.

I tried extending the transaction in testcase in this child class I added

function void pre_randomize()
 r_wn.rand_mode(0);
 r_wn = 1;
endfunction

created the object of this child class. Passed it to env.gen.trans = child object.

But still r_wn is not getting controlled this way.

Please help to drive the five trans packets from the test case(controlled at the top) such that r_wn=1 for that.

Thanks

2

In reply to pgoharani:
It would help if you

  • Used code tags in your posts to make them more readable. I have added them for you.
  • Showed a more complete example.