How to constraint a variable in extended class based on a variable in base class?

SystemVerilog
, ,
1

Below is an example I was trying. Even though the kind variable is being randomized to both II and IEEE, I see that in the extended class constraint, it only prints kind as II and thus keeps vlan variable as zero. Am i missing something here?

class macframe;
    typedef enum {II,IEEE} kind_e;
    randc kind_e kind;
    
    function display();
      $display("the kind is %p",kind);
    endfunction
  endclass
  
  class bvlan extends macframe;
    bit vlan=0;
    constraint myconstraint{
      if(super.kind == "II") vlan == 1;}
      
      function display();
        super.display();
        $write("%d",vlan);
      endfunction             
  endclass

module tb;
macframe mac;
bvlan vlanobj;  
  initial begin
    mac = new();
    vlanobj = new();
    repeat(10)
      begin
         mac.randomize();
         mac.display();
         vlanobj.display();
      end
   end
endmodule
2

In reply to yr:

Once again, please use code tags making your code easier to read. I have added them for you.

You have created two distinct objects and only randomized one of them. When you call vlanobj.display(), vlan still has its initial value.

Have you looked at this course yet?

3

In reply to dave_59:

Hi Dave , sorry about the tags. I will add them from next time.

I understand that i have randomized only one object. So when does the randomized value of kind be used to constrain the value of vlan? because even if i do the following , the initialized value of vlan which is zero is printing.

class macframe;
    typedef enum {II,IEEE} kind_e;
    randc kind_e kind;
 
    function display();
      $display("the kind is %p",kind);
    endfunction
  endclass
 
  class bvlan extends macframe;
    bit vlan=0;
    constraint myconstraint{
      if(super.kind == "II") vlan == 1;}
 
      function display();
        super.display();
        $write("%d",vlan);
      endfunction             
  endclass
 
module tb;
macframe mac;
bvlan vlanobj;  
  initial begin
    mac = new();
    vlanobj = new();
    repeat(10)
      begin
         mac.randomize();
        vlanobj.randomize();
         mac.display();
         vlanobj.display();
      end
   end
endmodule
4

In reply to yr:

Because you did not declare it as a random variable

rand bit vlan=0;