How the constraint is executed

SystemVerilog
1

Could you please help me how the constraint is being executed as variable a is declared in both classes

class first;
  rand bit [31:0] a;
  constraint con1 { a <100;}
endclass
class second extends first;
  rand bit [15:0] a;
  constraint con2 { a>50;}
endclass
2

In reply to srbeeram:

When you declare a class property with the same name in an extended class, you hide the visibility of the class property with same name in the base class from the extended class.

The constraint con2 applies a>50 to second::a, and the constraint con1 apples a<100 to first::a. So the two class properties ‘a’ get randomized and constrained independently. Note that if you had given the two constraints the same name, the constraint in the base class would become invisible to randomize(), and first::a would then be unconstrained.

It’s generally a very bad idea to extend a class and have class properties with the same name.