How to connect ports(which is defined as input or output array) when instantiate

SystemVerilog
,
1

hi guys,

i have a module A with port declaration as following:

module A #(NUM_SLAVES) (
input sig_a[NUM_SLAVEs]  
);

and there is another module B:

module B (
output sig_b;
);

then in my case, i set NUM_SLAVES=1, and connect sig_a of module A to sig_b of module B like:

module C ();
 B inst_b();
 A inst_A #(1)(
     .sig_a (inst_B.sig_b),
      ...
);
endmodule

i am using QuestaSim, compile is ok, but when it complains when loading design and log is :
Array connection type ‘wire’ is incompatible with ‘wire$[0:0]’ for port (sig_a): Can’t mix packed and unpacked types.

anyone can help?

2

In reply to philerpeng:

I don’t think you can use like that in verilog.
Please try:


// Module A
module A #(parameter NUM_SLAVES = 1) (
input [NUM_SLAVES-1:0] sig_a
);
endmodule

// Module B
module B (
output sig_b
);
endmodule

// Module C
module C ();
 wire sig;
 B inst_b(.sig_b(sig));
 A #(1) inst_A (.sig_a (sig));
endmodule
3

In reply to philerpeng:

Regardless of the value of NUM_SLAVES, your input port sig_a is an unpacked array expecting to be connected to an unpacked array, even if only one element. Unpacked arrays are stronger types than packed arrays which don’t care about number of matching bits in an assignment.

You need to use an array assignment pattern or a concatenation with the proper number of array elements:

     .sig_a ( { inst_B.sig_b } ),
4

In reply to chris_le:

thanks chris_le, module A is provided by VENDOR as constituent part of VIP, so we don’t need to modify it. Dave is correct, i just finished my trying according to his suggestion.

5

In reply to dave_59:

In reply to philerpeng:
Regardless of the value of NUM_SLAVES, your input port sig_a is an unpacked array expecting to be connected to an unpacked array, even if only one element. Unpacked arrays are stronger types than packed arrays which don’t care about number of matching bits in an assignment.
You need to use an array assignment pattern or a concatenation with the proper number of array elements:

     .sig_a ( { inst_B.sig_b } ),

thanks Dave, your suggestion is clear and correct.