How to connect with array port

SystemVerilog
1

module test（
input logic a[0:2]）;

logic x, y,z; //a[0]=x a[1]=y a[2]=z
test inst_test(
.a({x,y,z}) //solution1
.a('{x,y,z}) //solution2
);

which works ,or other way?

2

In reply to designer007:

{x,y,z} is a concatenation resulting in a 3-bit packed array
'{x,y,z} is a positional assignment for an array of 3 1-bit elements.

Since your input is an unpacked array of 3 1-bit elements, you want solution 2.