How to check the skew between output 2 lanes of an IP in system verilog?

SystemVerilog
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I want to check the skew between 2 lanes of an IP. Both are available as output ports for verification.

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In reply to epm333:

I believe the answer is the same as your other question: How to write a assertion to check no of pos edges of a clock within 120ns from trigger condition | Verification Academy