I want to check if some of my assertions are enabled or disabled. Is there a way to do that?
If I use a waveform viewer, are assertions supposed to be present on the hierarchy if they are enabled?
In reply to Reuben:
The assert ON/Off function does not impact the waveform viewer. If OFF, the trace will show no activities.
If you absolutely need to know this info, set a flag prior to turning the assert ON/OFF.
Ben. Systemverilog.Us
In reply to ben@SystemVerilog.us:
In reply to Reuben:
The assert ON/Off function does not impact the waveform viewer. If OFF, the trace will show no activities.
If you absolutely need to know this info, set a flag prior to turning the assert ON/OFF.
Ben. Systemverilog.Us
Okay, I see. That’s why I can still see those assertions in the waveform viewer even though they are already disabled. Anyway, I tried to check the simulation log file and the tool I’m using is flagging if the assertion has been turned off by $assertoff().