How to certify RTL working at last moment

SystemVerilog
,
1

90% verification done, after in RTL some changes went and without effect the previous results, how I can conclude now it’s working fine or not within one hour(Time limit)??

2

In reply to Subbi Reddy:

You have been to a lot of interviews. :grinning:

There are two technologies you could employ here.

  • Sequential Logic Equivalence Checking. If the changes are in a small enough area, formal equivalence checking gives you a quick exhaustive answer to whether thee functionality remains the same.
  • Test Plan Tracking (or Test Ranking). If you built up a suite of regression tests, testplan track can help you select the shortest tests to run to cover the functionality in the blocks that have been modified
3

In three interviews only asked lot of Questions :)
Test plan cracking was helpful for variables changes( two or more variables values changes)??