How to cast an instance's port?

Hi All,

I’m receiving the “Error (10928): SystemVerilog error at : enum type cannot be assigned to enum type - enum target requires cast” while compiling my code.

Here is the code:


typedef enum reg [31:0] {
  IDLE,
  LOAD,
  SHIFT}
rly_fsm_t;

rly_fsm_t state, nxt_state;

  rly_fsm #(.L                          (DW))                    
i_rly_fsm (// States
           .state                       (state),
           .nxt_state                   (nxt_state),
           // Inputs
           .clk                         (clk),
           .rstn                        (rstn),
           .go                          (cmd_rdy));

How can I fix it? How to cast an instance’s port?

Thank you!

In reply to dmitryldm:

How are the DUT ports state and nxt_state declared? Do they use a different enum type? If they do, then you should use that same enum type for your local variables.