How to capture assertion errors from RTL in the testcase PASS FAIL decision

SystemVerilog
,
1

I have an RTL design with assertions

When I run a testcase, assertion errors are reported, but my environment don’t have a way to count the assertion errors
It seems to me like I have to parse the log file and report any assertion errors been identified and report PASS FAIL on the top of test bench environment reported PASS/FAIL.

Is this the way or is there any other way to capture assertion errors from RTL in the testcase PASS FAIL decision

2

In reply to kvenkatv:
Tools report the number of times the assertions pass/fail.
You can use the action block to modify testbench variables that can be acted upon by the environment.


bit somev; // to be used by testbench 
ap_someP: assert property(@(posedge clk) someP) else somev=1'b1;

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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