How can we pass the generic values as in vhdl in the verilog?and how can we use the genric value in the slicing of the vector?

SystemVerilog
1

**actually i have to pass a generic value in the verilog code and then also use that generic value in the vector slicing…
for example if the generic value is TEST.
then we have to give it as the argument of a function and there we have to use a vector …
such that new_vec[TEST-4:0].
Now if i try to do something like this it gives the error that the index range should always be constant…
So what should i do to sort it out?
**

2

In reply to chaitanyh shirsh:
A generic in VHDL maps to a parameter in Verilog. And you can only use parameters and constants in specifying the width of a slice.

You should look for examples of mixing Verilog and VHDL in your tools directory, or search the web.