How can we implement virtual constructor functionality in system verilog?

While going through some websites I came across this question, since we cant define constructor as virtual, then Why do we need virtual constructor functionality and how can we implement it in system verilog?

In reply to Manoj J:

Think carefully about what you are asking. What would be the difference in behavior between a virtual and non-virtual constructor?

In reply to dave_59:

If I make the constructor as virtual then I am building the derived class without building the base class. But this is not allowed.
If the construtor is not virtual then first the base class will be built after that the derived class will be built. I can access the base class properties using derived class object/handle.

In reply to Manoj J:

In some case I want to allocate memory only for derived class but not for base class.
can we do like this?

In reply to Manoj J:

Virtual keyword in SystemVerilog is used when you want to override the base class’s function/task by derived class’s function/task (polymorphism). It doesn’t relate to how object is built/created.


If the construtor is not virtual then first the base class will be built after that the derived class will be built

When you create object of derived class, there is only one object located in memory, base class object will never be created.
Because derived class inherits attributes from base class, then in new constructor of derived class, we usually call super.new to build these attributes in base class.

The reason that SystemVerilog doesn’t allow virtual constructor, you can refer the following thread: Can we make constructor method virtual? | Verification Academy

In reply to chris_le:

Thank you chris_le !!