I have found a method to solve the problem.
Modify Interface as below, add 2 extra signals.
interface bidir(input clk);
assign wire_dp = dp;
assign wire_dm = dm;
In class task method(dynamic object), use dp|dm to procedure assignment and use wire_dp|wire_dm to sample.
But the code seems wierd.
In VCS, just define dp/dm as wire type, and procedure assignment and sample both can use the same net dp/dm. The interface is much more like the real environment(only 2 signals, not 4 signals).