How can i conditionally print display statement in assertion

SystemVerilog
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1

i have a sequence which i call when an assertion is triggered to check the consequence. i have a display statement in sequence but i dont want that display statement to print everytime like the option we have with UVM_VERBOSITY for info msgs. is there a way i can disable the display statement and only print when i set some parameter?

sequence req_ack_check_seq(string property_name,int r_num,int a_num,int min, int max,logic sig);
int l_num;
(1’b1,l_num=r_num,[b]$display($stime,“%0s :: Entering sequence local req_ack counter value is %0d”,property_name,l_num))__
##[min:max] ((sig==1 && a_num==l_num),$display($stime,“%0s :: Ack Arrived for local req_ack counter value %0d”,property_name,a_num));
endsequence

2

In reply to shahparth08:
You can call any task or void function upon matching a sequence and that includes uvm_report_info (you can’t use the `uvm_info macro directly because that expands to a block of code).

 sequence req_ack_check_seq(string property_name,int r_num,int a_num,int min, int max,logic sig);
  int l_num;
    (1'b1,l_num=r_num,uvm_report_info("seqmatch",$sformatf("%0s :: Entering sequence local req_ack counter value is %0d",property_name,l_num)),UVM_LOW,`__FILE__,`__LINE__)
      ##[min:max] ((sig==1 && a_num==l_num),$display($stime,,,"%0s :: Ack Arrived for local req_ack counter value %0d",property_name,a_num));
  endsequence