How to avoid "Too few instance port connections" error?

SystemVerilog
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1

Hi,

I’m cleaning the repo for a new project and I hit the “Too few instance port connections” error in my top module. These ports have been intentionally left unconnected. Hence I wanted to know how to make my compiler not throw these errors so that I get to know actual errors related to the functionality of my TB and some real bugs if at all present. If I don’t suppress these errors I will not be able to compile further.

Just for the sake of numbers, I have 25 ports unconnected out of 450 declarations.

Thanks

2

In reply to nimitz_class:

The best way to get rid of the port connection errors/warnings is using named port connections instead of positional. For example if your dut was

module DUT(input a,b, output c,d);
   ...
endmodule

Then you could use the following options to connect by name

module top;
  logic a,b,c,d;
  
  DUT dut(.a(a),.b() ,.c);
  
endmodule

Once you move away from positional connections any name you omit (like d) will not produce a message in most simulation tools. Other tools may still complain thought. You can also be explicit by using an empty set of parenthesis (like .b()).

If you really must use position port, then you can use extra commas, but this is very prone to errors is mismatched connections.

 DUT dut(a,,c,);