How to avoid race around in concurrent assertion

Below assertion checks if src_data has changed more than once before clock changes. I am observing a race around where src_data may have #0 glitch and assertion is false firing. How do I rewrite this?



property data_src_no_glitch (src_data, clk_dest, kill=0);
   logic data;
   @(src_data) disable iff (kill)
   (1,data = !src_data) |=> @(clk_dest) (src_data == data);
endproperty

In reply to vshankr:
Because you are observing a race around where src_data with a #0 glitch, you could use trigger an automatic task upon the detection of src_data transition. That task does a #0 to let the race condition settle, and then continue with the assertion.
Now, I am not sure if #0 will do the trick, that needs further analysis. If that #0 solution fails, use a #1, as shown in the comments.
Please let us know if that worked, and whether the #0 solution worked.


    always @(src_data) begin
        if(kill==0)
        fork 
         glitch_t();
        join_none
    end

    task automatic glitch_t();
        logic data; 
        #0; // May work, needs analysis
        data = $sampled(src_data);
        // #1; // If #0 does not work
        // data =  src_data;
        @(clk_dest);
        assert(src_data == data);
    endtask

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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