How to assign a variable name to a parameter?

SystemVerilog
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1

I’m working with a memory model. I’m looking for a way that the input of my register is a parameter. That parameter will hold the name of a variable.
This is what I did:


parameter PARAM_1 = wire_var;

This code above resulted in a compile error saying that wire_var is undefined. My parameters are in a separate file and I’m just including them in my memory model.
So I tried doing this below:


parameter PARAM_1 = "wire_var";

However, this resulted to a warning saying that the size of the input port of the register mismatches the size of the connected wire.


// Input ports
.triggerMask(PARAM_1), // This input port has a size of 1 bit

The size mismatch error says 64/1… When I analyze it, I think it’s because “wire_var” has 8 characters and each character is 8-bit in size, thus 8x8=64.

So, how do I make a parameter where I can pass the name of a variable?

My other question is, is there a way to make an array of defines?
The reason why I would like to use a parameter instead of defines is because I don’t know how to make an array of defines. Let’s say the array size is 1000. It’s impractical to create 1000 defines. So I chose using a parameter since I know how to make an array of parameters.

Thanks.

Regards,
Reuben

2

In reply to Reuben:
You can’t do what you are trying to do in SystemVerilog. Are the parameters that are defined in a separate file included in the same module where both the wire_var and the port connection are located? If so you may want to look at using the alias construct. Otherwise, you will need to explain in a lot further detail the situation that brought you to this.

And there is no way to create an array of `defines within SystemVerilog.

3

In reply to dave_59:
Hi,

I tried using the alias but a compile error says illegal operand for constant expression.
Here’s what I did:


// In this code, wire_var is triggerWrite0, while PARAM_1 is REGISTER_0_TRIGGER_WRITE
wire triggerWrite0;
assign triggerWrite0 = pm_trig[0];
alias triggerWrite0 = TRIG_WRITE0;
parameter REGISTER_0_TRIGGER_WRITE = TRIG_WRITE0; // Compile error points here

I’ll explain the situation in much further details later. I’m just looking for a better way to explain it simply.

Regards,
Reuben

4

In reply to Reuben:
I meant to use the alias statement instead of a parameter. Parameters can only represent two things, a value or a data type. And either must be fixed at compile time. You can’t use a parameter to select a signal like a mux. But you can use a mux to select a signal.

5

Parameters are evaluated at Elaboration time, not at zero simulation time. At elaboration time, the instances and connection between instances is formed. By connectivity, I mean checking port widths and ports existence etc. Since, the actual instances are created, parameters are also evaluated at elaboration time. Hence the parameters needs to be elaboration time constants (henceforth the error).

While, actual wire and regs comes into effect from zero simulation time onwards. So, you cannot assign a parameter the name from a reg/wire.

Refer to this thread for compile and elaboration times.

6

This is the situation: I have an array of registers. These registers have an input port called triggerWrite. This input port can be connected to one of these 3 wires - triggerWrite0, triggerWrite1, triggerWrite2. Now I want the users to be the one to specify to which wire they want this input port to be connected with. That’s why I chose to use a parameter.


wire triggerWrite0;
wire triggerWrite1;
wire triggerWrite2;
wire tieLow = 1'b0;

parameter TRIG_WRITE [0:255] = '{default : tieLow}; // This parameter is actually in a separate file.
                                                    // User can change this to choose which wire this parameter
                                                    // will be used for.

// Each of the register in the register array has this input port
generate
  for(genvar ii=0; ii<=255; ii++) begin
    Register#(/* Some parameters here*/) Register_00_to_FF (
       // Some ports here

       // This is the input port I'm talking about
       .triggerWrite(TRIG_WRITE[ii]), // If user did not specify, then default is tied to low
    );
  end
endgenerate

Anyway, Dave and sharvil, I think I have understood your points.
So as a solution to my problem I just did this:


wire triggerWrite0;
wire triggerWrite1;
wire triggerWrite2;
wire tieLow = 1'b0;

wire [255:0] reg_00_to_ff_trig_write;

parameter TRIG_WRITE [0:255] = '{default : 3};  // User can change this parameter to choose on the following:
                                                // 0 - connects to triggerWrite0
                                                // 1 - connects to triggerWrite1
                                                // 2 - connects to triggerWrite2
                                                // 3 or other - connects to tieLow

generate
  for(genvar ii=0; ii<=255; ii++) begin
    case(TRIG_WRITE[ii])
      0: assign reg_00_to_ff_trig_write[ii] = triggerWrite0;
      1: assign reg_00_to_ff_trig_write[ii] = triggerWrite1;
      2: assign reg_00_to_ff_trig_write[ii] = triggerWrite2;
      default: assign reg_00_to_ff_trig_write[ii] = tieLow;
    endcase

    Register#(/* Some parameters here*/) Register_00_to_FF (
       .triggerWrite(reg_00_to_ff_trig_write[ii]),
    );
  end
endgenerate