I am simulating my homebrew "TTL cpu" before building and want to put timings on my chips that somewhat reflect rthe real device.
The model below is for a 74HCT151.
I want to understand how realistic timings could be achieved in a verilog model.
The datasheet is https://assets.nexperia.com/documents/data-sheet/74HC_HCT151_Q100.pdf
What would a 74HCT151 with realistic timing behaviour look like?
Is any verilog modelling expert out there able to update this model to include realistic timing.
My initial attempt was using "inertial delays" but what I want for my simulation is "transport delays".
With inertial delays then small pulses on the inputs are suppressed by the interial delay type.
By using transport delays I hope to see a worst case scenario for the simulation - ie maximal glitches.
By having max glitches I hope to find flaws in the logic of the simulation that I can hope to avoid when I go to hardware.
My latest attempt at a simulation is https://www.edaplayground.com/x/kXAL
My reasoning for this approach is bug detection as mentioned here ....
"Although the Inertial Model is a more accurate reflection of reality than the Transport Delay model, it is possible to make a case for using the Transport Delay model for simulation. Strictly speaking, the purpose of digital simulation is not to create an accurate model of the real world. The purpose of digital simulation is to detect and correct bugs in a circuit. A short pulse which is only slightly shorter than the gate delay, may cause unpredictable results in the real circuit. The short pulse may be recognized as a change by some gates and not by others. The short pulse may behave differently in different copies Chapter 4:Multi-Delay Simulation 9 of the same circuit. In such a case, it is better to transmit the pulse than to filter it out. On the other hand, a circuit designer may decide to use a large slow gate as a filter for hazards that occur in preceding stages of the circuit. If such hazards cause the circuit to malfunction, the Inertial Model must be used to simulate the correct behavior of the circuit."
The basic logic without timings is as below ...
module hct74151(_E, I, S, Y, _Y);
output Y, _Y;
input [2:0] S;
input [7:0] I;
wire o =
(S==0 & I) ||
(S==1 & I) ||
(S==2 & I) ||
(S==3 & I) ||
(S==4 & I) ||
(S==5 & I) ||
(S==6 & I) ||
(S==7 & I);
assign Y = _E==0 ? o : 0;
assign _Y = !Y;
always @* begin
$display("%9t %m ", $time, "_E=%1b I=%8b S=%1d Y=%b _Y=%b ", _E, I, S, Y, _Y);