How to access internal wires from dut in WB assertions

Hi All,

I am going write assertions for some modules in dut.
Please let me know can i access internal wire/ reg from DUT(not ports) in my white box assertion file.

Thanks,
Nagendra.

See my DVCon paper:
https://verificationacademy.com/resources/technical-papers/the-missing-link-the-testbench-to-dut-connection