Ho to create Assertion checker for drain time of buffer and wake up time

SystemVerilog
1

Hi

I want to create a assertion checker for below cases.

Case1:- At x-time FC bit is asserted it will create backpressure to below pipeline, and for scheduled packets it will take some time to complete the transactions and after that we need to check salience in pipe.

Case2:- At y-time FC bit is de-asserted To schedule the packets it will take some time and after that we need to check transactions in pipe.

Please help on this assertions creations.

Thanks in advance.

Thanks,
Guru

2

In reply to GURUSWAMY S:

Hi,
Have you written assertions before or is this the first time you are writing them?

Siva