Is hierarchical referencing synthesizable?


// Inside an RTL module of a design
logic probe_this;

assign probe_this = sub_module1.sub_module2.sub_module3.signal_to_probe;

Is that code above will be synthesized together with the RTL codes inside that module?

In reply to Reuben:

I don’t think it is synthesizable. In order to access the sub-modules signals, one has to declare the signals as ports and connect them up to higher level. You can add output port from low level module and connect it in top level hierarchically.

As a side note, refer to some alternative for accessing out of scope signals for a module.

In reply to Reuben:

It depends. You certainly would not be able to preserve any hierarchy if there is reference that crosses the boundary. Best to ask on the forum of a tool that you are using.